Vertical-cavity surface-emitting lasers (VCSELs) are used in a variety of communication technologies, including short-wavelength multi-mode fiber optic communication systems. VCSELs are also effective and robust in extreme temperature and radiation environments, making them useful in applications such as illuminators and industrial thermal processing. Single VCSEL devices generally operate at optical output powers of several milliwatts, especially when designed for data rates of 10 Gb/s or higher. Larger optical output powers may be attained by building simultaneously-addressed arrays of VCSELs on common substrates or on multiple substrates.
However, VCSELs are limited to modest aperture sizes as a result of current spreading losses and modal properties. In order to scale VCSELs to higher power, the usual approach is to create an array of VCSELs on a common die. The arrayed devices are often combined in parallel or series, and designed for low modulation bandwidth. In parallel arrangements, multiple VCSELs on a single substrate are typically commonly connected through the wafer, and the lasers are electrically connected in parallel with a common cathode connection. Such configurations may be found, for example, in U.S. Pat. No. 7,949,024 B2, which describes parallel configurations of back-emitting VCSEL arrays. However, additive bulk capacitance is a limiting factor for parallel operation of VCSELs, and parallel arrangements may not be the ideal impedance match to high current pulsed driver circuits. R. Carson, M. Warren, P. Dacha, T. Wilcox, J. Maynard, D. Abell, K. Otis, and J. Lott, “Progress in high-power high-speed VCSEL arrays,” Proc. SPIE 9766, Vertical-Cavity Surface-Emitting Lasers XX, 97660B (18 Mar. 2016), has shown that much higher optical power can be attained by connecting multiple die in series. Each of the individual die has multiple VCSELs that are connected in parallel, but then the sub-mount that the die are flip-chip bonded to can connect the die in series.
Series-connected VCSEL arrays have been shown to greatly enhance the output optical power at a given current relative to a single parallel-connected VCSEL array, especially when operated from a low duty-cycle pulsed current source. Such high power pulsed light sources are particularly useful for applications such as flash-LiDAR and short range NIR illumination.
In many current series-connected configurations, each VCSEL array comprises a set of parallel VCSEL elements arranged on a single chip, or wafer, and a common cathode path, formed by shorted contacts, that connect to a conduction layer on the chip. Multiple chips are bonded on a common sub-mount and arranged to form a series connection. In a flip-chip arrangement, each chip's anode is connected to common electrical connections on the sub-mount, and the common cathode connection on each chip connects to the next chip's anode connection on the sub-mount arrangement. Since such configurations use a common cathode arrangement on each chip, “tiling” multiple chips on the common sub-mount has been the only way to realize a series connection configuration.
The approach of “tiling” has many advantages from the standpoint of design flexibility. However, there are configurations where using a single chip is significantly more advantageous. For example, in laser assemblies where segmented groups of micro-lenses are used, the relative alignment accuracy between those lenses is critical such that relative angular differences between the tiled chips become problematic. Another example is the case where there is a low-value current source that could benefit from the extra optical power associated with series connection, but the extra semiconductor die area required for tiling multiple die causes cost and packaging issues.
Tiling also requires extra real estate, and multiple chips can lead to increased costs and packing issues. Thus, in some cases, such size, cost, and manufacturing factors outweigh the advantages of extra optical power associated with a series connection. Furthermore, since the matched properties are more likely to come from VCSEL elements mounted on the same chip, tiling may not be preferable when wavelength control requirements dictate that the VCSEL elements used in the series connection have nearly identical emission properties.